An 8-bit CPU emulator build with HTML, CSS, and JavaScript. The CPU has 4 multi-purpose registers (R0, R1, R2, R3),
that can be used to store any 8-bit value. In addition to this, there is also 256 slots of 8-bit SRAM that can be rewritten to
and accessed as the program runs. It can be accessed through the READ (RD) and SAVE VALUE (SAV) instructions.
Type your code in the Programming Area and then click the "Run Code" button to run the
code and view it's output in the Program Output Area.
The PRT (print) instruction has been added to easily allow for character printing. The PRT
instruction takes in N to print as a number or an A to print the character mapped to the ASCII code.
A newline can be printed by loading 10 into a register and printing it out as ASCII.
Program Cycles: 0
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Instruction | Syntrax |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | BREAK | BRK |
| 0 | 0 | 0 | 1 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | AND | AND Rd, Rr |
| 0 | 0 | 1 | 0 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | OR | OR Rd, Rr |
| 0 | 0 | 1 | 1 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | XOR | XOR Rd, Rr |
| 0 | 1 | 0 | 0 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | ADD | ADD Rd, Rr |
| 0 | 1 | 0 | 1 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | SUB | SUB Rd, Rr |
| 0 | 1 | 1 | 0 | Rd[1] | Rd[0] | 0 | 0 | SHIFT LEFT | SL Rd, Value |
| 0 | 1 | 1 | 0 | Rd[1] | Rd[0] | 0 | 1 | SHIFT RIGHT | SR Rd, Value |
| 0 | 1 | 1 | 0 | Rd[1] | Rd[0] | 1 | 0 | NEGATIVE | NEG Rd |
| 0 | 1 | 1 | 0 | Rd[1] | Rd[0] | 1 | 1 | LOAD | LD Rd, Value |
| 0 | 1 | 1 | 1 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | READ | RD Rd, Rr |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | JUMP | JMP Label |
| 1 | 0 | 0 | 1 | C | N | Z | O | JUMP FLAG | JPF Flag, Label |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CALL | CALL Label |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | RETURN | RET |
| 1 | 0 | 1 | 0 | Rd[1] | Rd[0] | 1 | Type | PRT Rd, T | |
| 1 | 0 | 1 | 1 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | BRANCH EQUAL | BRQ Rd, Rr, Label |
| 1 | 1 | 0 | 0 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | BRANCH GREATER | BRG Rd, Rr, Label |
| 1 | 1 | 0 | 1 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | BRANCH LESS | BRL Rd, Rr, Label |
| 1 | 1 | 1 | 0 | Rd[1] | Rd[0] | Rr[1] | Rr[0] | SAVE VALUE | SAV Rd, Rr |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | NO OPERATION | NOP |